1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating an MIM capacitor, by which a dual-stack structure can be provided using a general logic forming process.
2. Discussion of the Related Art
FIGS. 1A to 1F are cross-sectional diagrams for explaining a capacitor fabricating method according to a related art.
FIG. 1A shows a step of forming a first conductive layer and an insulating layer on a semiconductor substrate.
Referring to FIG. 1A, a first insulating film 1 for insulation from devices below is stacked on a semiconductor substrate on which the FEOL process of a semiconductor device (i.e., transistor formation) has been performed in a general manner. The first insulating layer 1 is then planarized. A first metal layer 2 is stacked on the resultant structure after planarization and is then patterned by photolithography. A second insulating layer 3 is stacked on the resultant structure after photolithography and etching, and the insulating layer 3 is then planarized by CMP or the like.
FIG. 1B shows a step of forming a via hole and stacking a second metal layer.
Referring to FIG. 1B, the second insulating layer 3 is etched to form a via hole 5 over the first metal layer 2 by photolithography. Metal is deposited on the substrate to fill up the via hole, and the deposited metal is planarized. Then, a second metal layer 6 is deposited on the second insulating layer 3 including the metal filling the via hole 5. A portion of the second metal layer 6 will be used as a lower electrode of a capacitor. In doing so, the second metal layer 6 contains a multi-layer including Ti/TiN/Al_Cu/Ti/TiN or the like.
FIG. 1C shows a step of stacking a dielectric layer and an upper electrode layer of a capacitor.
Referring to FIG. 1C, a dielectric layer 7 to be used as a dielectric of a capacitor and a third metal layer 8 to be used as an upper electrode of the capacitor are stacked over the substrate in turn. Namely, the dielectric layer 7 is formed 500˜1,000 Å thick by depositing a SiN layer by PECVD. And, the third metal layer 8 is deposited on the dielectric layer 7 over the substrate to be used as the upper electrode of the capacitor. In doing so, the third metal layer 8 contains a multi-layer including Ti/TiN.
FIG. 1D shows a step of patterning an upper electrode of a capacitor.
Referring to FIG. 1D, photoresist is coated over the substrate. The photoresist is patterned into a photoresist pattern 9 defining an upper electrode by exposure and development. The third metal layer is then etched using the photoresist pattern 9 as an etch mask.
FIG. 1E shows a step of patterning a lower electrode of the capacitor.
Referring to FIG. 1E, after the photoresist pattern has been removed from the structure shown in FIG. 1D, photoresist is coated on the resultant structure. Exposure and development is carried out on the photoresist to form another photoresist pattern 10 defining a lower electrode 14 and a second level of metallization 15. The second metal layer is then etched using the photoresist pattern 10 as an etch mask.
FIG. 1F shows a step of forming wires of the upper and lower electrodes of the capacitor.
Referring to FIG. 1F, after the photoresist pattern 10 in FIG. 1E has been removed, a third insulating layer 11 as an interlayer is stacked over the substrate. Via holes 12 of the upper and lower electrodes are formed by photolithography. Finally, wires 13 of the upper and lower electrodes are formed on the third insulating layer 11 including the via holes 12.
However, the related art capacitor fabricating method cannot increase the size of the capacitor to provide sufficient capacitance for certain applications without undue area consumption.